Scheda insegnamento (lingua inglese)

Scheda insegnamento (lingua inglese)

Stampato il 19.05.2024 ore 18:26

Title

Metodologia della sintesi logica
Methodology of Logic Synthesis

Degree

Corso di Laurea in Ingegneria Elettronica
First Level Degree in Electrical Engineering

Year

Teaching Period

Credits

Teacher: Mirko Loghi

Academic year: 2009/2010

Objectives:

The class introduces the main techniques for the analysis and synthesis of combinational and sequential logic networks.

Requirements:

Acquired skills:

Understand the terminology and mathematical theory to model digital logic.
Analyze the behavior of combinational and sequential logic networks.
Derive from informal specifications the truth table of a combinational function, minimize and realize it with two-level logic.
Derive from informal specifications the state diagram of a finite state machine, minimize, encode and realize it with combinational logic and memory elements.

Lectures and exercises		hours
Topics	Specific contents
Introduction to modern logic design		4
Boolean algebra		6
Two-level and multi-level minimization		6
Complex combinational networks		2
Programmable logic and memories		2
Arithmetic circuits		4
Delay in combinational circuits		2
Sequential networks		6
Complex sequential networks		2
Delay in sequential circuits		2
Finite state machines		4
Design of sequential systems		4
Total hours for lectures and exercises		44
for exercises only
Further educational activities		hours
Labs		6
Tutorials / Seminars
Workshops
Guided tours

Total hours for further educational activities		6
Total hours		50

Type of exam: Written

References:

R. H. Katz, "Contemporary Logic Design", Addison Wesley Publishing Company, Reading, MA, 1993.
Fummi, Sami, Silvano, "Progettazione digitale"

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