| Lectures and exercises |
hours |
| Topics |
Specific contents |
|
| The logical effort design methodology |
Definition of the model; applications; optimization of chains of digital blocks; branching; forks. |
10
|
| Interconnects |
Scaling rules for interconnects; Capacitive models of an interconnect; RC models of interconnects; Elmore's formula; inductive effects; lossless transmission lines; terminatino techniques |
10
|
| Semiconductor memories |
Classification; internal organization; ROM; SRAM; DRAM; Non volatile memories (EPROM, EEPROM, FLASH) |
10
|
| Implementation of digital designs |
Implementation of digital designs: full custom, semicustom. Cell based and array based designs. Standard cells, macrocells, compiled cells, gate arrays, sea of gates, programmable logic devices |
3
|
| Circuits for programmable logic devices |
Fuses and Antifuses, multiplexers, logic block, programmable interconnects. FPGA. |
3
|
| Simulation |
Usage of basic simulation tools (PSPICE and Microwind) to exemplify the digital design flow. |
4
|
| Total hours for lectures and exercises |
40 |
| for exercises only |
|
|
Further educational activities
|
hours
|
| Labs |
8 |
| Tutorials / Seminars |
2 |
| Workshops |
|
| Guided tours |
|
| |
|
| Total hours for further educational activities |
10 |
| Total hours |
50
|