The class main object is to study and analyze the main techniques for the design of modern high-performance computers. Starting from the pre-requisites of the design of the modern instruction sets, the focus moves on identifying the main techniques for the realization of the processors. During the class, the approach followed assumes that instruction set and processor realization are highly correlated topics. Main object of the techniques that are illustrated is to reduce as much as possible the penalization due to the processor hardware structure, aiming at an execution model where the execution order is no longer embedded in the source code, but more carried by the way the information is processed conforming to the elaboration flow design by the software designer. In this way it is possible to realize systems able to automatically extract the intrinsic instruction level parallelism (ILP) by means of architectures that allow the simultaneous execution of multiple instruction during the same clock period. The class will illustrate general purpose processors’ applications (RISC and Intel architectures), together with applications for specific processor (such as embedded processors, DSP, graphical and multimedia processors, I/O processors). In the last par, the class will show the main lines along which the next generation processor will develop, as far as algorithmic approach is concerned (such as VLIW architectures) and also concerning non algorithmic architectures (such as neural and fuzzy processors).